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Что (кто) такое victim cache - определение
victim cache
SPECIAL CACHE USED IN MODERN MICROPROCESSORS
<architecture> An extension to a direct mapped cache that
adds a small, secondary, fully associative cache to store
cache blocks that have been ejected from the main cache due to
a capacity or conflict miss. These ejected blocks are likely
to be needed again so storing them in the secondary cache
should increase performance.
Victim caches with as few as five places have been found to
reduce conflict misses, especially for small, direct-mapped
data caches. E.g. a four-place victim cache removed 20% to
95% (depending on program) of such misses in a 4-KB cache.
http://www.scism.sbu.ac.uk/ccsv/josephmb/CS-L2-MT/week12.html.
(2007-02-23)
Victim cache
SPECIAL CACHE USED IN MODERN MICROPROCESSORS
A victim cache is a small, usually fully associative cache placed in the refill path of a CPU cache that stores all the blocks evicted from that level of cache, originally proposed in 1990. In modern architectures, this function is typically performed by Level 3 or Level 4 caches.
secondary cache
![Austek]] A38202; to the right of the processor)](https://commons.wikimedia.org/wiki/Special:FilePath/Motherboard Intel 386.jpg?width=200 "Austek]] A38202; to the right of the processor)")
![[[Motherboard]] of a [[NeXTcube]] computer (1990). At the lower edge of the image left from the middle, there is the CPU [[Motorola 68040]] operated at 25 [[MHz]] with two separate level 1 caches of 4 KiB each on the chip, one for the instructions and one for data. The board has no external L2 cache.](https://commons.wikimedia.org/wiki/Special:FilePath/NeXTcube motherboard.jpg?width=200 "[[Motherboard]] of a [[NeXTcube]] computer (1990). At the lower edge of the image left from the middle, there is the CPU [[Motorola 68040]] operated at 25 [[MHz]] with two separate level 1 caches of 4 KiB each on the chip, one for the instructions and one for data. The board has no external L2 cache.")
DYNAMICALLY MANAGED LOCAL MEMORY THAT MIRRORS MAIN MEMORY IN A MICROPROCESSOR TO REDUCE THE COST OF ACCESS
Level 1 cache; Level 2 cache; Cache line; CPU memory cache; Trace Caches; Trace caches; Cache block; Cache-line; L2 cache; L3 cache; L1 cache; CPU caches; CPU Cache; Data cache; Internal cache; Data Cache; First-level cache; L2-Cache; L1-Cache; Second-level cache; Secondary cache; Tag RAM; Direct mapped; Cpu cache; Instruction cache; L2 Cache; Cache flush; Motherboard cache; Discrete L2 cache; Level 3 cache; VIVT; VIPT; I cache; Processor cache; Internal and external cache; Multi-ported Cache; Smart Cache; CPU cache line; Copy-back; L4 cache; Micro-operation cache; Uop cache; Last level cache; Last Level Cache; Cache eviction; Exclusive CPU cache; Inclusive CPU cache; Exclusive cache; Inclusive cache; Multi-level cache; Multilevel cache; On-chip cache; Cache lines; Shared cache; Non-blocking cache; Branch target cache; Branch target instruction cache; SmartCache; Smart cache; L1d
<memory management> (Or "second level cache", "level two
cache", "L2 cache") A larger, slower cache between the
primary cache and main memory. Whereas the primary cache
is often on the same integrated circuit as the {central
processing unit} (CPU), a secondary cache is usually external.
(1997-06-25)
Википедия
Victim cache
A victim cache is a small, usually fully associative cache placed in the refill path of a CPU cache that stores all the blocks evicted from that level of cache, originally proposed in 1990. In modern architectures, this function is typically performed by Level 3 or Level 4 caches.
